|CEVA in the News|
Below is a list of webinars relating to CEVA technologies
Optimizing DSP cores for Performance and Power with DesignWare Logic Libraries and Embedded Memories (256 B)
DSP cores occupy a key role in System-on-Chips (SoCs) targeting a wide range of end products, from smartphones and wearable devices, to wireless infrastructure. Depending on the application, these core implementations may target high or low speeds but they always seek to optimize area and power dissipation. In this webinar, CEVA and Synopsys will present results and best practices in hardening DSP cores to achieve performance targets while consuming low power and using minimal area in target applications, using DesignWare® Logic Libraries and Memory Compilers on a 28-nm process, along with Synopsys' implementation and signoff tools. CEVA will also show how choosing the correct IP and methodology helps achieve optimal results and overcome physical design bottlenecks.
The trend of using computer vision techniques for innovative embedded applications is a widespread reality. Initially used in industrial and security applications, it is now widely used in automotive applications (mostly for car safety systems), smartphones and tablets (for unique real-time applications and gaming), as well as to Smart TVs (for gesture recognition and other natural UI). Moreover, some of the cutting-edge imaging applications, such as super resolution, advanced super scaling and HDR are using techniques from the computer vision space. The main challenge for SoC and application developers is providing powerful computer vision capabilities combined with SW flexibility, while meeting the stringent power constraints of embedded applications. Using a vector processor such as the CEVA-MM3101, with an instruction set specifically tuned for embedded vision, makes computer vision a reality.
Trends and challenges of voice/audio pre and post processing in smartphones, tablets and mobile computing devices (256 B)
With the growing demand for clearer, better-intelligible and noise-tolerant voice communication in smartphones and mobile devices, the DSP voice processing tasks are increasingly complex. Audio processing has become more demanding as well with >100h of audio playback time, and ample post-processing requirements for improved sound. In addition to increased complexity and higher performance, cost and power consumption must be addressed as well, to allow for a competitive solution. This webinar will review the growing mobile voice and audio processing complexities (wide-band codecs, multi-microphone noise reduction, speaker compensation and other post-processing), and trends in recent handsets such as the iPhone4S. A market proven solution based on the CEVA-TeakLite-III DSP family and the Alango voice processing SW package, to address these challenges shall also be reviewed.
Addressing HD Audio IC complexity - Considerations for DSP selection and audio subsystem design (256 B)
With the growing complexity of home entertainment audio, such as very high bit-rates, loosless codecs, and advanced audio post-processing, designers of multimedia SoCs are faced with increased challenges. In addition to high performance, cost must be addressed as well, to allow for a competitive solution. This webinar will describe the complexities of HD Audio in applications such as DTV, Set-Top-Box, and Blu-ray Disc, and will provide an overview of the CEVA-TL3211 DSP core and the way it effectively addresses HD Audio codecs and audio subsystem design challenges.
Designing a 4G Multi-mode Wireless Baseband for Infrastructure Applications - From Femtocells to Macrocells (256 B)
With the rapidly growing demand for increased data rates, operators are forced to quickly upgrade their networks by adapting to 3.5G and 4G standards (HSPA+, LTE and WiMAX). Traditionally, operators built their wireless networks around conventional base station architectures. With the introduction of Femto-cells, operators will be able to build a heterogeneous network hierarchically using: Femto, Pico, Micro and Macro cells. This evolving base station topology forces substantial challenges upon equipment manufactures to offer wireless broadband devices, with high sensitivity to cost. The OEMs are looking for new ways to significantly lower their development costs, in order to achieve a lower MSRP and meet the operators budget. This webinar will offer a fresh approach for designing advanced 4G solutions targeting the various network equipment devices.
This webinar will describe efficient implementation of HD-Audio applications by using the CEVA-TL3210 DSP Core. It will start with a description of the requirements for HD-Audio in Blu-ray Disk and Digital TV applications. This will be followed by a description of the CEVA-TL3210 DSP core features and capabilities. Afterwards, an explanation on how CEVA-TL3210 is used for the most intensive and complex HD-Audio use-cases in the Multimedia market. A detailed description of each use-case and its performance characteristics will conclude the session.
Addressing the Design Challenges of High Definition (HD) Audio and Other Consumer Applications with a 32-bit DSP Engine (256 B)
High-end audio applications such as HD DVDs, Digital TVs, Set-top Boxes and A/V Receivers are becoming an enormous challenge for DSP engines. With next generation HD audio codecs, such as Dolby Digital Plus 7.1 and DTS-HD, and the growing requirement for multi-stream decoding, a mere 16-bit DSP becomes an inadequate solution for these growing processing requirements. In addition, low power and small die size are still mandatory requirements when developing chips for such applications. To address these design challenges and provide the much needed performance improvements, CEVA has introduced CEVA-TeakLite-III, a new native 32-bit TeakLite-compatible architecture. In this webinar, you will learn how to address the design challenges of next generation High Definition (HD) Audio applications and other consumer applications such as multi-channel VoIP gateways and low-cost multimode handsets and advanced portable audio devices, using the new CEVA-TeakLite-III DSP. This webinar will reveal the insides of a 32-bit DSP that is both powerful enough to support 4 simultaneous Dolby Digital Plus streams and small enough to fit into any portable embedded solution.
With Serial ATA and Serial Attached SCSI rapidly taking over from their parallel predecessors, many designers are looking to integrate these serial storage interfaces into their next generation SoC. Join us as we attempt to highlight some of the important factors for consideration when facing such a challenge.
Choosing the right DSP for your next generation products is a far-reaching and critical decision. The programmable DSP is a key element in most SoC systems and it must take into account the architecture features offered by the DSP and the ability to provide the best performance solution for your needs including performance, frequency and power consumption. Today additional critical decisions in DSP choice include availability of complete tool chain, the ability to write efficiently in a high level C language and to use third parties software. Finally, the quality of the DSP IP for SoC design could be the difference between first pass success and failure. It is important to have a clear and strong road map in choosing a DSP, especially a licensable DSP. This decision is not only for one current product, but also future generation products that will reuse your software code and applications