|CEVA in the News|
LTE-Advanced represents the next generation mobile broadband, and in turn throws the challenge to the designers to create highly power efficient mobile devices capable of delivering these services. ARM, the leading supplier of embedded processors, physical IP and inter-connect fabric, along with CEVA propose a joint analysis looking at the design considerations that are required to realize the next generation of mobile wireless broadband devices.
This paper presents steps for real-time deployment of face detection application on a programmable vector processor. The steps taken are general purpose in the sense that they can be used to implement similar computer vision algorithms on any mobile device.
The evolution of 4G wireless baseband indicates there are two evolving technologies that are currently competing for the leading position; namely LTE and WiMAX. It is unclear which standard will eventually prevail, and it is highly possible that both standards will coexist and serve different use-cases in different geographies. To ensure that both of these standards are supported in 4G modems, a flexible solution that would allow for specific implementations under both technology roadmaps is required.
The CEVA-TeakLite-III is a 32-bit licensable DSP processor core from CEVA that builds on the legacy of the CEVA-TeakLite, CEVA-TeakLite-II, and CEVA-Teak cores. CEVA-TeakLite-III targets a range of portable and high-definition audio applications, along with VoIP and cellular baseband. BDTI recently completed an independent analysis of the CEVA-TeakLite-III core. In this paper, BDTI presents benchmark results for the CEVA-TeakLite-III that quantify its speed, power efficiency, and area efficiency relative to those of several competitors, and analyzes its strengths and weaknesses.
Embedded Systems Europe - May 2009. Eran Briman describes the powering of advancements in communications and multimedia technologies
Compared to current W-CDMA networks that support data rates of 2Mbit/s with additional rates improvements for HSPA, 4G modems will require almost a twenty-fold increase in processing horsepower. Designing a powerful and cost-effective communications IC that meets these stringent power constraints poses a fundamental challenge to the SoC designers.
Advances in video streaming and image rendering technologies have created exceptional High Definition moving image quality. Together with the increasing popularity of home entertainment centers, these have been significant drivers in the pursuit of the "movie theater" experience at home, or on portable electronic devices. This white paper will review different high definition delivery media, discuss the design challenges for IC designers and propose solutions and approaches for efficient HD audio implementation.
Know your hardware! That's what it's all about. Using programming guidelines derived from the processor's architecture can dramatically improve performance of C applications. In some cases, it can even make the difference between having the application implemented in C and having it implemented in assembly. Well written C code and an advanced compiler that utilizes various architectural features often reach performance results similar to those of hand written assembly code. A quick survey of assembly coding drawbacks should make it fairly clear why real-time programmers need architecture oriented programming guidelines in their toolkit.
As DSP processors become more powerful and compiler optimization techniques improve, the once common trend of writing DSP applications solely in assembly has withered away. Today, almost every DSP application is comprised of a combination of both C code and assembly code. In critical functions, where performance is of the essence, DSP engineers continue to use highly optimized assembly code. Less critical functions, however, are now written in C, allowing easier maintenance and better portability. This combination of C and assembly code requires special tools and methodologies in the tool box of every DSP engineer.
As DSP processors become more and more powerful, the portion of code that can remain at the C level increases. However, compilers cannot produce optimized code without assistance from the programmer. To maximize the performance, the programmer must tune the compiler using various compilation options.
Unfortunately, it is quite common to find DSP applications that don’t take advantage of the tuning capabilities of the compiler. Instead, they are compiled with the same set of compilation options throughout the whole application. This method ignores the special needs of each function.
Smart selection of compilation options can yield a dramatic performance improvement. For example, it can greatly reduce code size, which is often a major factor when evaluating the cost of a product, as it has a direct influence on the amount of memory required. This article shows how to improve code size consumption as well as the consumption of other important resources.
The ever increasing demands of multimedia processing capabilities from handset, PDA and other multimedia device manufacturers, and the escalating chip costs, are pushing the boundaries of silicon design. While hard-coded solutions were effective for one or two multimedia formats, the market is demanding that multiple formats and codecs be supported by the same design, to give a comprehensive and user-friendly experience to device owners. But as the audio, video and imaging formats became more numerous, the hard-coded paradigm was becoming cumbersome and ineffective.
The need for a fully programmable software solution is rapidly being understood by major handset manufacturers as the key to successful deployments of multimedia devices in the coming years. By reusing the same platform for multiple designs and devices, Mobile-Media bridges the gap between the escalating cost and design cycles, and the decreasing revenues and product life cycles.